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mos integrated circuit the m pd16431a is an lcd controller/driver that enables display of segment type lcds of 1/2, 1/3, or 1/4 duty cycle. this controller/driver has 56 segment output lines of which eight can also be used as led output lines. because the lcd driver contained in the m pd16431a has separate logic and power supply, up to 6.5 v of lcd drive voltage can be set. in addition, key source output lines for key scanning and key input data lines are also provided, so that the m pd16431a is ideal for applications in the front panel of an automobile stereo system. features ? various display modes 1/2 duty: 112 segment outputs or 96 segment outputs + 8 led outputs 1/3 duty: 168 segment outputs or 144 segment outputs + 8 led outputs 1/4 duty: 224 segment outputs or 192 segment outputs + 8 led outputs ? key scan circuit (key source outputs are shared with lcd driver outputs) ? independent lcd driver power supply v lcd (can be set to v dd to 6.5 v) ? serial data input/output (sck, stb, data) ? on-chip oscillator incorporated ? power-on reset circuit ordering information part number package m pd16431agc-7et 80-pin plastic qfp (0.65 pitch, 14 14) m pd16431a 1/2, 1/3, 1/4-duty lcd controller/driver printed in japan document no. ic-3414 (o.d. no. ic-8885) date published january 1995 p 1995 data sheet
m pd16431a 2 block diagram s 1 /ks 1 s 1 /ks 2 s 8 /ks 8 s 48 segment driver 48 56 level shifter (56) 56 selector circuit 56 output latch (56 4) 56 56-bit shift register s 56 /led 8 8 s 49 /led 1 led driver oe 8 common driver com 1 com 4 4 4 level shifter oe lcd/led sync timing generator osc 2 read address i/o control write address key counter 8-bit shift register 8 command decoder key counter osc in osc out key 1 key 4 key latch s/r key req clk data stb v dd v ss v lcd v lc1 v lc2 v lc3
m pd16431a 3 pin configuration seg 36 seg 35 seg 34 seg 33 seg 32 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 /ks 8 seg 7 /ks 7 seg 6 /ks 6 seg 5 /ks 5 seg 4 /ks 4 seg 3 /ks 3 seg 2 /ks 2 seg 1 /ks 1 com 4 com 3 com 2 com 1 40 21 41 60 v ss key 1 key 2 key 3 key 4 key req sck data stb lcd/led oe osc in osc out sync v dd v lcd v lc1 v lc2 v lc3 v ee 61 80 20 1 seg 37 seg 38 seg 39 seg 40 seg 41 seg 42 seg 43 seg 44 seg 45 seg 46 seg 47 seg 48 seg 49 /led 1 seg 50 /led 2 seg 51 /led 3 seg 52 /led 4 seg 53 /led 5 seg 54 /led 6 seg 55 /led 7 seg 56 /led 8 note though v ss and v ee are internally connected, be sure to connect all the power supply pins (v dd , v ss , v lcd , and v ee ).
m pd16431a 4 pin functions symbol seg 1 /ks 1 to seg 8 /ks 8 seg 9 to seg 48 seg 49 /led 1 to seg 56 /led 8 com 1 to com 4 sck data stb lcd/led oe note osc in osc out sync key 1 to key 4 key req v dd v ss v lcd v ee v lc1 to v lc3 note at oe = l, the key data cannot be written correctly, even when the display on/off of the status command is set to the normal operation (10). also, in this state, unnecessary waveforms are generated from between seg 1 /ks 1 to seg 8 /ks 8 during the key scanning period. (the display is off.) name segment output/key source output segment output segment output/led output pins common output shift clock input data input/output strobe input lcd/led select output enable input oscillation input oscillation output synchronizing signal key data input key request output logic power supply logic gnd lcd drive power supply lcd gnd power supply for lcd drive no. 25 to 32 33 to 72 73 to 80 21 to 24 7 8 9 10 11 12 13 14 2 to 5 6 15 1 16 20 17 to 19 description these pins serve as lcd segment output pins and key source output pins for key scanning. lcd segment output pins these pins can be used as lcd segment output or led output pins depending on the setting of the lcd/led pin. lcd common output pins data shift clock. data is read at the rising edge, and is output at the falling edge of this clock. this pin inputs a command or display data, or outputs key data. a command or data is input at the rising edge of the shift clock, starting from the most significant bit. key data is output at the falling edge of the shift clock, starting from the most significant bit. this pin serves as an open-drain pin in the output mode. data can be input when this signal goes low. when it goes high, command processing is performed. when this signal goes high, the seg n /led m pins function as lcd segment output pins; when it goes low, they function as led driver output pins. the led driver has a drive capability of 15 ma and is n-ch open drain. when this signal goes low, all the segment output and led output pins are off (seg n = com n = v lcd ). internal data are saved. connect a resistor for oscillation circuit across these pins. a synchronizing signal input pin. when two or more m pd16431as are used, each device is wired-ored. this pin must be pulled up when this chip is used alone. key data input pins for key scanning this signal goes high when a key is pressed (key data = h). read the key data only while this pin is high. power supply pin for internal logic gnd pin for internal logic and led output power supply pin for lcd drive gnd pin for lcd drive power supply for driving dot matrix lcd
m pd16431a 5 configuration of shift register two shift registers, an 8-bit command register and a 56-bit display register, are provided. the first 8 bits of input data are recognized as a command and are sent to the command register, and the 9th bit and those that follow are recognized as display data and are sent to the display register. b7 command 8-bit shift register b0 msb lsb seg 56 /led 8 display data (lcd, led) 56-bit shift register seg 1 msb lsb transfer direction the meaning of the display data is as follows: lcd: 0 ? off, 1 ? on led: 0 ? on, 1 ? off be sure to transfer 56 bits of display data. configuration of output latch seg 56 /led 8 seg 1 msb lsb com 1 (latch address note : 00) seg 56 /led 8 seg 1 com 2 (latch address note : 01) seg 56 /led 8 seg 1 com 3 (latch address note : 10) seg 56 /led 8 seg 1 com 4 (latch address note : 11) note bits b3 and b4 of status command (refer to page 8.)
m pd16431a 6 key matrix configuration an example of key matrix configurations is shown below. 1) when pressing three or more times is assumed: a configuration example is shown below. in this configuration, 0 to 32 on switches can be recognized. key 1 key 2 key 3 key 4 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 ks 1 = c 2) when pressing twice or more times is assumed: a configuration example is shown below. in this configuration, 0 to 2 on switches can be recognized. key 1 key 2 key 3 key 4 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 ks 1 = diode a in this configuration, pressing three or more times may cause off switches to be determined to be on. for example, if sw2 to sw4 are on and ks 1 has been selected (high level) as shown below, sw3 in which current i 1 is running is supposed to be detected to be on. however, since sw2 and sw4 are on, current i 2 runs thus resulting in sw1 to be recognized as being on. key 1 key 2 key 3 key 4 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 select ks 1 sw3 sw4 i 1 i 2 = sw1 sw2
m pd16431a 7 if diode a is not available, not only the key data may not be read normally but the lcd display may be affected or ics may be damaged or deteriorated. for example, if sw1 and sw2 are on and ks 1 has been selected (high level) as shown below, this will cause not only current i 1 which is supposed to run but also short-circuited current i 2 of ks 1 to ks 2 to run. it is possible that this will then cause the following three problems: (1)since the level to key 2 is not correctly sent, the key data cannot be latched correctly. (2)if ks 2 is used as seg 2 as well, the lcd display may be distorted (such as causing unintended segments to light up). (3)since the short-circuited current (current i 2 ) of ks 2 (high level) to ks 2 (low level) runs, ics may be damaged or deteriorated key 1 key 2 key 3 key 4 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 select (high level) non select (low level) ks 1 sw1 sw2 i 1 i 2 =
m pd16431a 8 configuration of key data latch the key data is latched as illustrated below and is read by a read command, starting from the most significant bit. key data is read once a frame and latched when coinciding with the immediadtely preceding data. in other words, it requires at least 2 frames from the time the key is pressed till data is confirmed to be the key data (the key request becoming h). 32-bit latch/shift register ks 1 msb lsb ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 key 1 key 2 key 3 key 4 the key data is 0 when off and 1 when on. key input equivalent circuit key n to key latch pull-down control signal ?the pull-down control signal goes high only during key source output and turns on the pull-down transistor. ?the on-resistance of the pull-down transistor is several k w .
m pd16431a 9 command a command sets a display mode and a status. the first 1 byte input after the stb pin has fallen is regarded as a command. if the stb pin is made low while a command/data is transferred, serial communication is initialized, and the command/data being transferred is made invalid (the command/data that has been already transferred remains valid, however). (1) display setting command this command initializes the m pd16431a and sets a duty cycle, frame frequency, drive voltage supply method, test mode, and whether the m pd16431a operates as the master or a slave. when this command is executed, display is forcibly turned off and key scanning is stopped. to resume the display, the normal operation of the status command must be executed. note, however, that nothing is executed if the same mode is selected. b0 msb lsb b1 b2 b3 b4 b5 b6 0 sets duty. 00: 1/4 duty, 1/3 bias 01: 1/3 duty, 1/3 bias 10: 1/2 duty, 1/2 bias 11: 1/2 duty, 1/2 bias sets frame frequency. 00: (f osc /128) n 01: (f osc /256) n 10: (f osc /512) n 11: (f osc /1024) n n= duty (1/2, 1/3, 1/4) sets drive voltage supply method. 0: internal 1: external sets master or slave. 0: master 1: slave sets test mode. 0: normal operation 1: test mode 0 values when power is applied 0 0 0 0 0 0
m pd16431a 10 (2) status command this command sets a data write/read mode, turns on/off display, and sets a latch address. b0 msb lsb b1 b2 b3 b4 1 sets data write/read mode. 0: writes display data to output latch 1: reads key data turns on/off display 00: forcibly turns off display (all segments and leds off). stops key scanning. 01: prohibited 10: normal operation 11: don? care sets latch address. 00: com 1 01: com 2 10: com 3 11: com 4 0 values when power is applied 0 0 0 0 : don? care
m pd16431a 11 top : with internal power supply bottom: with external power supply output select voltage 1. com + C bias when selected v lcd gnd 1/2 bias v lcd gnd when not selected 1/2 v lcd 1/2 v lcd v lc2 v lc2 when key scanned 1/2 v lcd 1/2 v lcd v lc2 v lc2 when selected v lcd gnd 1/3 bias v lcd gnd when not selected 1/3 v lcd 2/3 v lcd v lc3 v lc1 when key scanned 1/2 v lcd 1/2 v lcd v lc2 v lc2 2. seg + C bias when selected gnd v lcd 1/2 bias gnd v lcd when not selected v lcd gnd v lcd gnd when key scanned gnd v lcd gnd v lcd when key not v lcd gnd scanned v lcd gnd when selected gnd v lcd 1/3 bias gnd v lcd when not selected 2/3 v lcd 1/3 v lcd v lc1 v lc3 when key scanned gnd v lcd gnd v lcd when key not v lcd gnd scanned v lcd gnd
m pd16431a 12 output waveform (1) 1/2 duty (1/2 dias) * k 0 * k 1 * k 0 * k 1 * k 0 0101 v lcd v lc2 v lcd v lc2 v lcd v lc2 v ee v ee v ee v lcd v lc2 v ee v lcd 1/2v lcd 0 -1/2v lcd -v lcd v lcd 1/2v lcd 0 -1/2v lcd -v lcd com 1 com 2 seg 1 seg 9 seg 1 -com 1 seg 1 -com 2 1 key req (w/key) 2 key req (w/key w/o key) 3 key req (w/o key w/key) *: key scan period (16/fc)
m pd16431a 13 key scan period (k0) expansion 1k0 0 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 seg 2 seg 3 seg 4 seg 5 -seg 40 = key source output
m pd16431a 14 key scan period (k1) expansion 0k1 1 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 -seg 4, seg 9 -seg 40 seg 5 seg 6 seg 7 seg 8 = key source output 1 key req (w/key) 2 key req (w/key w/o key) 3 key req (w/o key w/key)
m pd16431a 15 (2) 1/3 duty (1/3 bias) * k 0 * k 1 * k 2 * k 0 * k 1 0120 v lcd v lc2 v lcd v lc2 v lcd v lc2 v ee v ee v ee v lcd v lc2 v ee v lc1 v ee com 1 com 2 com 3 seg 1 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lcd v lc3 v lc2 v lcd 1/2v lcd 1/3v lcd -1/2v lcd -1/3v lcd 0 seg 1 -com 1 -v lcd v lcd 1/2v lcd 1/3v lcd -1/2v lcd -1/3v lcd 0 seg 1 -com 2 -v lcd seg 9 *: key scan period (16/fc)
m pd16431a 16 key scan period (k0) expansion 2k0 0 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 seg 2 seg 3 seg 4 seg 5 -seg 8 = key source output v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3
m pd16431a 17 key scan period (k1) expansion 0k1 1 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 -seg 4, seg 9 -seg 40 seg 5 seg 6 seg 7 seg 8 = key source output v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3
m pd16431a 18 key scan period (k2) expansion 1k2 2 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 -seg 40 v lc1 v lc3 v lc1 v lc3
m pd16431a 19 (3) 1/4 duty (1/3 bias) * k 0 * k 1 * k 2 * k 3 * k 0 0123 v lcd v lc2 v lcd v lc2 v lcd v lc2 v ee v ee v ee v lcd v lc2 v ee v lc1 v ee com 1 com 2 com 3 seg 1 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lcd v lc3 v lc2 v lcd 1/2v lcd 1/3v lcd -1/2v lcd -1/3v lcd 0 seg 1 -com 1 -v lcd v lcd 1/2v lcd 1/3v lcd -1/2v lcd -1/3v lcd 0 seg 1 -com 2 -v lcd v lcd v lc2 v ee v lc1 v lc3 com 4 * k 1 0 2/3v lcd -2/3v lcd -2/3v lcd 2/3v lcd seg 9 *: key scan period (16/fc)
m pd16431a 20 key scan period (k0) expansion 3k0 0 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 seg 2 seg 3 seg 4 seg 5 -seg 40 = key source output v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3
m pd16431a 21 key scan period (k1) expansion 0k1 1 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 -seg 4, seg 9 -seg 40 seg 5 seg 6 seg 7 seg 8 = key source output v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3 v lc1 v lc3
m pd16431a 22 key scan period (k2) expansion key scan period (k3) expansion 1k2 2 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 -seg 40 v lc1 v lc3 v lc1 v lc3 2k3 3 1 2345678 v lcd v lc2 v ee v lcd v lc2 v ee com 1 seg 1 -seg 40 v lc1 v lc3 v lc1 v lc3
m pd16431a 23 serial communication format (1) receive (command/data write) stb data b7 b6 b5 b2 b1 b0 sck 123 678 if data continues (2) transmit (command/data read) stb data 7 6 5 sck 123 2 1 678 7 6 123 4 3 456 5 0 data read command set wait time t wait data read 1 s m note because the data pin is an n-ch open-drain output pin, be sure to connect an external pull-up resistor to this pin (1 k w to 10 k w ).
m pd16431a 24 application 1. example of initial setting + display data write parameter stb command/data remarks b7 b6 b5 b4 b3 b2 b1 b0 start h set display command l 00000000 1/4 duty, frame frequency = fosc/128 1/4, internal drive voltage, master h status command l 1 0 0 0 0 0 0 0 display data write, display off, latch address: com 1 display data 1 l com 1 data (7 bytes) display data 7 l h status command l 1 0 0 0 1 0 0 0 display data write, display off, latch address: com 2 display data 1 l com 2 data (7 bytes) display data 7 l h status command l 1 0 0 1 0 0 0 0 display data write, display off, latch address: com 3 display data 1 l com 3 data (7 bytes) display data 7 l h status command l 1 0 0 1 1 0 0 0 display data write, display off, latch address: com 4 display data 1 l com 4 data (7 bytes) display data 7 l h status command l 1 0 0 0 0 1 0 0 display data write, display on end h ? ? ? ? ? ? ? ? ? ? ? ?
m pd16431a 25 2. example of display data write (rewrite, 1/4) parameter stb command/data remarks b7 b6 b5 b4 b3 b2 b1 b0 start h status command l 1 0 0 0 0 1 0 0 display data write, display on, latch address: com 1 display data 1 l com 1 data (7 bytes) display data 7 l h status command l 1 0 0 0 1 1 0 0 display data write, display on, latch address: com 2 display data 1 l com 2 data (7 bytes) display data 7 l h status command l 1 0 0 1 0 1 0 0 display data write, display on, latch address: com 3 display data 1 l com 3 data (7 bytes) display data 7 l h status command l 1 0 0 1 1 1 0 0 display data write, display on, latch address: com 4 display data 1 l com 4 data (7 bytes) display data 7 l end h ? ? ? ? ? ? ? ? ? ? ? ?
m pd16431a 26 3. example of key data read parameter stb command/data remarks b7 b6 b5 b4 b3 b2 b1 b0 key req check key req = h: key data exists. ? start reading. key req = l: key data does not exist (reading is inhibited). ? check key req again. start h status command l 1 0 0 0 0 1 0 1 data read, display on wait time l 1 m s key data 1 l 4 bytes key data 4 l end h ? ? ?
m pd16431a 27 absolute maximum ratings (t a = 25 ?c, v ss = 0 v) parameter symbol ratings unit logic supply voltage v dd C0.3 to +7.0 v logic input voltage v in C0.3 to v dd + 0.3 v logic output voltage (data) v out C0.3 to +7.0 v lcd drive supply voltage v lcd C0.3 to +7.0 v lcd drive supply input voltage v lc1 to v lc3 C0.3 to v lcd + 0.3 v driver output voltage v out2 C0.3 to v lcd + 0.3 v (segment, common, led) led output current i o +20 ma operating ambient temperature t opt C40 to +85 ?c storage temperature t stg C55 to +150 ?c permissible package power p t 1 000 mw dissipation recommended operating conditions parameter symbol min. typ. max. unit logic supply voltage v dd 2.7 5.0 5.5 v lcd drive supply voltage v lcd v dd 5.0 6.5 v logic input voltage v in 0 v dd v driver output voltage v lc1 to v lc3 0v lcd v
m pd16431a 28 electrical specifications (unless otherwise specified, t a = C40 to +85 ?c, v dd = v lcd = 5 v 10%) parameter symbol min. typ. max. unit input voltage, high v ih 0.7 v dd v dd v input voltage, low v il 0 0.3 v dd v input current, high i ih clk, stb, lcd/led, oe 1 m a input current, low i il clk, stb, lcd/led, oe C1 m a output voltage, low v ol1 led 1 to led 8 . i ol1 = 15 ma 1.0 v output voltage, high v oh2 osc out , i oh2 = C1 ma 0.9 v dd v output voltage, low v ol2 data, osc out , sync, i ol2 = 4 ma 0.1 v dd v leakage current, high i loh2 data, sync, v in out = v dd 1 ma leakage current, low i lol2 data, sync, v in out = v ss C1 ma common output on resistance r com com 1 to com 4 , | i o | = 100 m a 2.4 k w segment output on resistance r seg seg 1 to seg 56 , | i o | = 100 m a 4.0 k w logic current dissipation i dd f osc = 250 khz 250 m a lcd drive current consumption i lcd with internal bias and no load 500 m a remark the typ. value is a reference value at t a = 25 ?c.
m pd16431a 29 switching characteristics (unless otherwise specified, t a = C40 to +85 ?c, v dd = v lcd = 5 v 10%, r l = 5 k w , c l = 150 pf) parameter symbol conditions min. typ. max. unit oscillation frequency f osc r = 100 k w 175 250 325 khz oscillation frequency f osc r = 200 k w 105 150 195 khz propagation delay time t pzl sck ? ? data ? 100 ns propagation delay time t plz sck ? ? data 300 ns sync delay time t dsync 1.5 m s timing requirements (unless otherwise specified, t a = C40 to +85 ?c, v dd = v lcd = 5 v 10%, r l = 5 k w , c l = 150 pf) parameter symbol conditions min. typ. max. unit clock frequency f c osc in external clock 50 325 khz high-level clock pulse width t whc osc in external clock 1.5 16 m s low-level clock pulse width t wlc osc in external clock 1.5 16 m s shift clock cycle t cyk sck 900 ns high-level shift clock pulse t whk sck 400 ns width low-level shift clock pulse t wlk sck 400 ns width shift clock hold time t hstbk stb ? ? sck ? 1.5 m s data setup time t ds data ? sck 100 ns data hold time t dh sck ? data 200 ns stb hold time t dkstb sck ? stb 1 m s stb pulse width t wstb 1 m s wait time t wait clk ? clk ? 1 m s sync removal time t srem 250 ns output load output v dd 5 k w 150 pf
m pd16431a 30 v il t wlc v ih t whc 1/f c csc in t hkstb v il stb t wstb v ih v il sck t whk t wlk t cyk v ih t dh t ds v ih v il data sync f osc internal reset t dsync t srem sync timing (master) sync timing (slave) 1 frame 1 frame 1 frame 1 frame switching characteristic waveform
m pd16431a 31 switching characteristic waveform v il t pzl sck v ol2 t plz data application circuit example (with led, 1/4 duty, 1/3 bias) data sck stb key req oe lcd/led sync. osc in osc out key n led n seg 48 seg 9 to seg 8 /ks 8 seg 1 /ks 1 to pd16431a m v dd v ss v lcd v lc1 v lc2 v lc3 v ee com n 4 lcd 8 40 8 8 4 r 8 led r 5 r 7 r 6 r 1 r 2 r 2 r 1 gnd +6 v +5 v gnd to microcomputer key matrix 8 4 r 1 : 1 k to 10 k w r 2 : 1/2 r 1 r 5 , r 6 : 1 k to 10 k w r 7 : 100 k w typ. r 8 : 330 to 1 k w r 1 through r 2 are not necessary when the internal drive voltage is selected (v lc1 through v lc3 are open). v dd v lcd v dd
m pd16431a 32 note example of external source circuit (when 1/2 bias) v dd v ss v lc0 v lc1 v lc2 v lc3 v ee +5 v gnd +6 v gnd r 1 r 1 r 1 = 1 k to 10 k w (approx.) the application circuits and their parameters are for references only and are not intended for use in actual design-in's.
m pd16431a 33 80 pin plastic lqfp ( 14) item millimeters inches d f g k i j 0.825 0.825 1.00.2 0.65 (t.p.) 0.13 16.00.2 q 0.6300.008 0.032 0.032 0.039 0.005 0.026 (t.p.) s80gc-65-7et-1 note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. c 14.00.1 0.551 m 0.125 0.005 0.1250.075 0.0050.003 +0.004 C0.002 +0.005 C0.004 a 16.00.2 0.6300.008 h 0.300.10 0.012 +0.004 C0.005 l 0.50.2 0.020 +0.008 C0.009 n 0.10 0.004 p 1.40.1 0.0550.004 s 1.7 max. 0.067 max. +0.10 C0.05 b 14.00.1 0.551 +0.005 C0.004 r3 3 +7 C3 +7 C3 +0.009 C0.008 a f detail of lead end b g h ij c d p n k l m 41 60 40 61 21 80 20 1 m s q r
m pd16431a 34 reference document name document no. nec semiconductor device reliability/quality control system iei-1212 quality grade on nec semiconductor devices iei-1209 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11

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